INGI Seminar - On the Dynamic Compilation and Optimization of Packet Processing Programs

A recent innovation in data plane technologies is programmable switch pipelines, whereas switches adopt a reconfigurable data plane, like a programmable ASIC (Intel FlexPipe, RMT), NPU (Cavium XPA), or a software library (Intel DPDK), that can implement a great variety of different packet processing behaviors.  In this context, there is a separate data plane compiler (OpenFlow, P4, POF) translating from a high-level description of the intended switch behavior to the low-level packet processing primitives exposed by the target platform.  In this talk, we describe a new approach to data plane compilation, dynamic data plane compilers, that actively alter, optimize, or even completely rewrite packet processing programs on-the-fly in order to maximize the efficiently of the resultant data plane.

The standard approach to OpenFlow program compilation is a static one: build a unified OpenFlow data path that can support all OpenFlow programs, as downloaded by the controller into the switch at runtime, with reasonable efficiency.  This results in all sorts of performance regressions, since there is essentially no software datapath that could support, say, both an L2-heavy and an L4-intensive workload with the same efficiency, even though both could be triggered by the controller at runtime.  A dynamic approach to OpenFlow compilation would easily solve this problem, by runtime-specializing OpenFlow programs into the most efficient software implementation possible.

We introduce ESwitch, a new dynamic OpenFlow software switch compiler that uses on-the-fly template-based code generation to transform any OpenFlow program into actual x86 machine code that can then be directly used as a fast-path.  This way, ESwitch automatically identifies and optimizes typical workloads, compiling an L2-heavy OpenFlow program into an optimal Ethernet switch, an L3-intensive workload into an LPM engine, etc.  We present a proof-of-concept prototype and we demonstrate on illustrative use cases that ESwitch yields a simpler architecture, superior packet processing speed, improved latency and CPU scalability, and predictable performance.

We identify three elementary dynamic compilation and runtime-optimization techniques we use in ESwitch: template-based code generation, dynamic match-table optimization, and extensive just-in-time compilation.  We elaborate on these techniques to some degree and we make an initial attempt at generalizing these techniques beyond OpenFlow, to the broader context a hypothetical dynamic P4 compiler.

This is an extended version of the talk I gave at SIGCOMM 2017.

Gábor Rétvári received the M.Sc. and Ph.D. degrees in electrical engineering from the Budapest University of Technology and Economics (BME), Budapest, Hungary, in 1999 and 2007, respectively. He is now a Senior Research Fellow at the Department of Telecommunications and Media Informatics, BME.  His research interests include routing and switching in packet networks, switch and router design, clouds and software-defined networks, and the networking applications of information theory and computational geometry.  He is a Perl hacker, maintaining numerous open source scientific tools written in Perl, C and Haskell.